The present invention relates to an interface method for use in a digital signal processing system and a device for implementing the method. More particularly the invention relates to an interface method and device for transmitting data and control signals according to the rules on the corresponding receiving terminals in the digital signal processing system. A memory is used to store the corresponding data before transmitting predetermined data to the final data receiving terminal.
FIG. 1, which is a block diagram of the conventional digital signal processing system, shows a mini disc regenerating device.
Referring to FIG. 1, a servo controlling part 9 controls the driving of a feed motor 5 and a spindle motor 7. A pick-up part 3 receives an RF (Radio Frequency) signal from a disc 1. RF amplifier 11 amplifies the RF signal input from the pick-up part.
An EFM (Eight to Fourteen Modulation) decoder 15 having construction similar to the signal processing part of a conventional CD (Compact disk) decodes an output signal input from the RF amplifier part 11, and then stores the decoded signal in a memory 17. The memory 17 is controlled by a SRMC 19 (Shock Resistance Memory Controller).
Digital data stored in the memory 17 is outputted in units of sound groups of 212 bytes by a data request signal of an ATRAC (Adaptive Transform Acoustic Coding) decoder 21 under the control of the SRMC 19. Since an error flag indicating whether the digital data contains an error or not is stored in the memory 17, the error flag is outputted with the digital data.
The ATRAC decoder 21 is supplied with data in units of sound groups output from the SRMC 19 and outputs the sound group data to a digital/analog convertor 23 by expanding the sound group data to the original data.
A system controller 27 controls the servo control 9, the EFM decoder 15, the SRMC 19, the ATRAC decoder 21 and a display/key inputting part 25.
FIGS. 2A to 2D show a data organization scheme employed in the digital signal processing system shown in FIG. 1.
The data organization on the mini disc is shown in FIG. 2A. One cluster having 36 sectors is the fundamental unit of a recording operation. One cluster has 32 sectors for audio data and 4 sectors for sub data. During recording, three sectors of the 4 sectors for sub data are assigned to a link sector L and only one sector is assigned to the sub data sector S.
As shown in FIG. 2B, one sector has 2352 bytes. The audio data has 2332 bytes, which is 20 bytes subtracted from 2352 bytes, and can be recorded in one sector. The 20 bytes are the sum of a sync pattern consisting of 12 bytes and a header consisting of 8 bytes. The 2332 bytes consist of 5.5 sound groups. Each of the sound groups has 424 bytes, as shown in FIG. 2C.
Further, one sound group shown in FIG. 2D has 212 bytes in each of the right and left channels. The sound group becomes the fundamental unit of the process of the ATRAC decoder 21. The 424 bytes are obtained from 512 samples (11.61 msec).
FIG. 3 is a block diagram showing a data transmission process of the conventional object interface part shown in FIG. 1. FIGS. 4A to 4E are a timing diagram of an input/output signal of an output interface part 33 (hereafter, called "output I/F part" for short) shown in FIG. 3.
The timing diagram of the output I/F part 33 shown in FIGS. 4A to 4E, indicates a transmission cycle of data consisting of 1 word. The output I/F part performs the transmission cycle 106 times so that the 212 bytes are transmitted.
In FIGS. 3 and 4A to 4E, if a data transmission request signal XRQ shown in FIG. 4B is inputted to the output I/F part 33 from the object interface part (not shown), data corresponding to a read address is outputted to the output I/F part 33 from the memory 17 in response to the data transmission request signal XRQ shown in FIG. 4B. Then, the output I/F part 33 transmits serial data in units of bytes to the object interface part, and then outputs a synchronizing pulse shown in FIG. 4D. A bit clock (about 177 nsec) shown in FIG. 4A is 128 times as large as a sampling frequency FS.
After expanding in the object interface part 21, the transmission data shown in FIG. 4C is applied to the digital/analog convertor 23. The error flag is outputted from the memory 31 and is transmitted for each byte. For example, an error flag which is at the high state indicates that an error was generated in the transmission data.
If the data transmission request signal XRQ is at the high state in the falling edge of the synchronizing pulse of a second byte, the synchronizing pulse of the second byte becomes a rising edge, so that the transmission operation of data corresponding to one word is ended. The output I/F part 33 performs the cycle 106 times, repeatedly.
However, according to the conventional interface method for transmitting audio data to the object interface part, whenever one word is transmitted to the object interface part, the output I/F part 33 should check the data transmission request signal XRQ.
Further, according to the conventional interface method, it is also difficult to classify the channel of the audio data of 212 bytes. That is, it is difficult to classify that the audio data is stored either in the right channel (hereafter, called "R-CH" for short) or in the left channel (hereafter, called "L-CH" for short).